Low power, process and temperature insensitive FET bias circuit

ABSTRACT

A bias circuit for an FET switch in which a pinch-off voltage is generated and sets up a current through a first resistor. The current is reflected through a second resistor to establish a voltage differential across the second resistor which is then imposed across the gate-source terminals of the switch FET when it is desired to turn the switch OFF. The relationship of the turn-off voltage imposed across the switch FET to its pinch-off voltage is determined by the ratio of the resistance values of the two matched resistors, which ratio is independent process and temperature. The switch bias circuit thus offers highly reliable operation and at the same time a greatly reduced power consumption.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to electrical circuits, and more particularly toa bias circuit for a field effect transistor (FET) switch implemented asan integrated circuit.

2. Description of the Prior Art

In the past, inefficient biasing circuits have been utilized for FETswitches in order to provide tolerances for various circuit parameterswhich have been found to vary due to processing and temperatureconditions. These bias circuits have been designed to allow for worstcase conditions, and therefore consume considerably more power thanwould ordinarily be required.

FIG. 1 shows a typical prior art bias circuit for a junction FET (JFET)switch. This circuit has been utilized in the Precision Monolithics,Inc. SSS7510/7511 Quad SPST BI-FET Analog Switch. In this circuit JFET1functions as a switch element, with the remainder of the circuitryproviding a bias to ensure proper switching of JFET1.

The bias circuit includes JFET2, which has its gate and source terminalsconnected together to a positive bias voltage line V⁺ and provides asource of bias current at its drain. The drain current of JFET2 isdirected through a series of diode-connected transistors D1, D2 and D3.The base of D3 is connected to the base of a bipolar transistor Q1,whereby Q1 mirrors the current through D3. Q1 serves as a current sourcefor a differential switch having a left branch transistor Q2 and a rightbranch transistor Q3. The collector of Q2 is connected back to thepositive voltage bus through a resistor R1, while the collector of Q3 isconnected to the positive voltage bus through diode-connectedtransistors D4 and D5. Another current source JFET3 has its gate andsource connected to the positive voltage bus to provide a source ofcurrent for input transistor Q4, the base of which receives a logicinput signal at terminal 2.

The source of switch JFET1 is connected to the positive voltage busthrough diode-connected transistor D6 and a bipolar transistor Q5, thecollector of which is connected to V⁺ and the base of which is connectedto the opposite end of R1 from V⁺. The base of JFET1 is connected bylead 4 to the junction of D4 and Q3.

In operation, the common connection between the gate and source of JFET2provides a current at the drain of that element. This current isdelivered through D3 and mirrored by Q1 to provide a current source forthe differential switch Q2-Q3. Assuming it is desired to turn JFET1 OFF,a positive voltage signal is applied to base terminal 2 of Q4, turningthat transistor OFF and gating Q2. The base voltage of Q2 exceeds thethreshold voltage at the base of Q3 established by its connection to D1,causing the current from Q1 to flow through Q2 and R1 rather thanthrough Q3. The current through R1 establishes a voltage differentialacross the element with respect to V⁺ which is reflected to the sourceof JFET1, with two diode voltage drops through the base-emitter of Q5and D6. The gate of JFET1 in the meantime is held at a constant voltagelevel by D4 and D5, two diode drops below V⁺. By selecting the circuitelements to generate a pinch-off (V_(p)) voltage across R1, the sameV_(p) is established across the gate and source terminals of JFET1,turning it OFF.

To switch JFET1 ON, the gating voltage is removed from terminal 2,turning Q4 ON and Q2 OFF. This causes the differential switch current toflow through Q3, removing the voltage differential across R1. The gateand source of JFET1 are accordingly fixed at substantially equalvoltages, turning the switch ON.

Theoretically, JFET1 will be kept OFF so long as the voltage across R1is greater than V_(p). However, the various circuit elements of FIG. 1are subject to process and temperature variations that have resulted inR1 being assigned a much lesser resistance value than would be necessaryin the absence of such variations. This in turn has caused an excessivepower consumption when the differential switch current is routed throughR1.

The processing and temperature variations show up in several ways.First, R1 is typically subject to processing variations of up to 20% ormore, and in the Precision Monolithics, Inc. device referred to abovehas a temperature coefficient of 2000 ppm/°C.

The voltage across R1 may be expressed as follows: ##EQU1## whereI_(DSS) is the maximum drain current of JFET2, β, W and L arerespectively the device constant, width and length of JFET2, and V_(p)is the pinch-off voltage of JFET1 and JFET2. W is relatively constant,but L is usually sensitive to masking and etching, and β and V_(p) bothvary with processing and temperature. The net processing variations towhich I_(DSS) is subject can be in the range of 9:1, and I_(DSS) issubject to further temperature variations.

Accordingly, the voltage across R1 must be made large enough toaccommodate all expected variations and still generate an adequate V_(p)to turn JFET1 OFF. With a nominal V_(p) of 1.9 volts, the voltage acrossR1 has typically been set at 7 or 8 volts. R1 thus consumes about 3 to 4times more power than would be necessary if processing and temperaturevariations could be substantially eliminated, permitting the voltageacross R1 to be established at a level only slightly greater than V_(p).

SUMMARY OF THE INVENTION

In view of the above problems associated with the prior art, the objectof the present invention is the provision of a novel and improved biascircuit for an FET switch which consumes only a small amount of power,and yet operates reliably depsite both processing and temperaturevariations in the parameters of individual circuit components.

Another object of the invention is the provision of a novel and improvedbias circuit for an FET switch in which the V_(p) applied to the switchelement is determined by the resistance ratio of a pair of matchedresistors, and by another FET which is matched with the switch FET.

The above objects are accomplished by the provision of a bias circuitwith a control FET which is matched with the switch FET. Means areprovided for generating V_(p) across the gate and source of the controlFET. The switch and control FETs are interconnected by a circuit whichestablishes a voltage across the gate-source terminals of the switch FETwhich is at least as great as the voltage across the gate-sourceterminals of the control FET, whereby the generation of V_(p) across thecontrol FET automatically produces at least V_(p) across the switch FET.A switch control means interrupts the interconnection between thecontrol FET and switch FET in response to a switch actuation command.

The voltage generated across the control FET is applied to a firstresistor to produce a current which is reflected through a secondresistor in the interconnecting circuit between the control and switchFETs. The second resistor is connected in circuit with the switch FET soas to impose a voltage across the gate-source terminals of that elementwhich is at least equal to the voltage across the first resistor. Thesecond resistor is matching with the first resistor and preferably has aslightly greater resistance, thereby producing a voltage slightlygreater than V_(p) across the switch FET when the switch control meansis appropriately gated. This assures that the switch FET is completelyOFF in response to an appropriate logic control signal.

These and other objects and features of the invention will be apparentto those skilled in the art from the following detailed description,taken together with the accompanying drawings, in which:

DESCRIPTION 0F THE DRAWINGS

FIG. 1 is a schematic diagram of the prior art bias circuit for a FETswitch described above; and

FIG. 2 is a schematic diagram of an FET switch bias circuit constructedin accordance with the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Referring to FIG. 2, an improved bias circuit for an FET switch is shownwhich substantially eliminates the need to apply an excessive voltageacross the gate-source terminals of a switch FET to compensate forpossible processing and temperature variations, as was the case in theprior art. Numerous elements in the improved circuit of FIG. 2correspond to elements of the prior art circuit of FIG. 1; correspondingelements are indicated by the same reference characters and numerals inthe two figures.

The general approach taken in the improved circuit is to generate V_(p)independent of the switch FET, and impose the V_(p) thus generated ontothe switch FET when it is desired to turn the switch OFF. The V_(p) isimposed across the switch FET by means of a circuit which operatessubstantially independent of processing and temperature variations. Inthe embodiment shown in FIG. 2 this is accomplished by the provision ofa V_(p) generating circuit comprising JFET4 and transistor Q6. JFET4 ismatched with JFET1 and has its gate connected directly to the V⁺ line,its source connected to the collector of Q6 and also through a resistorR2 to the V⁺ line, and its drain connected to the base of Q6. An outputcurrent is provided from the emitter of Q6, which is connected to theinput of D1.

The circuit consisting of JFET4 and Q6 has been used in the prior art togenerate a V_(p), and is disclosed in an article by Adib R. Hamade andJose F. Albarran, "A JFET/Bipolar 8-Channel Analog Multiplexer," IEEEJournal of Solid-State Circuits, December, 1975, pp. 399-406. In thepresent invention it is utilized to generate a V_(p) which is reflectedacross the gate-source terminals of JFET1 when it is desired to turnthat element OFF.

The combination of JFET4 and Q6 generates a voltage at the source ofJFET4 and collector of Q6 which is less than V⁺ by V_(p). Thus, avoltage differential equal to V_(p) appears across R2, producing acurrent through that element which is directed through thecollector-emitter circuit of Q6 and on through D1, D2 and D3. Thecurrent through D3 is mirrored by Q1 and steered through either Q2 or Q3as determined by the input signal at input terminal 2, in a mannersimilar to the operation of the circuit of FIG. 1. The remainder of thedifferential switch circuit is similar to that of FIG. 1, except for anew resistor R3 which is substituted for R1 in the Q2 branch. R3 isproportionately matched with R2 and preferably has a slightly greaterresistive value. Since Q1 provides a 1:1 current mirror with D3, thecurrent through R3 will be substantially equal to the current through R2when Q2 is gated, thereby producing a voltage drop across R3 which hasthe same proportion to the voltage drop across R2 as does the resistivevalue of R3 to R2.

The voltage drop across R3 is reflected across the gate-source terminalsof switch JFET1 by means of Q5 and D6 which connect one end of R3 to thesource of JFET1, and D4 and D5 connecting the opposite end of R3 to thegate of JFET1. Since the voltages at the opposite ends of R3 bothundergo a 2-diode voltage drop in transit to the gate-source terminalsof JFET1, the voltage differential is preserved.

The resistance value of R3 is preferably 1.2 or so times the resistivevalue of R2. This ensures that the voltage imposed across thegate-source terminals of JFET1 will be slightly greater than V_(p) whenthe switch is to be turned OFF. At the same time the resistance value ofR3 is considerably greater than the resistance of R1 in the FIG. 1 priorart circuit, resulting in a marked decrease in power consumption.

The operation of the circuit of FIG. 2 will now be described, assuminginitially that JFET1 is ON. In this configuration a low voltage switchcontrol signal has been applied to the base terminal 2 of Q4, turningthe transistor ON and turning Q2 OFF. V_(p) is generated across R2 byJFET4 and Q6, producing a current which flows through R2, Q6, D1, D2 andD3, and is mirrored by Q1 and steered through the right-handdifferential switch branch consisting of Q3, D4 and D5. Sincesubstantially no current flows through R3 no appreciable voltage isestablished across that element, and the gate and source of JFET1 areboth held at substantially the same voltage level two diode drops belowV⁺, holding JFET1 ON.

Assuming that it is now desired to turn JFET1 OFF, a high voltage levelis applied to terminal 2, turning Q4 OFF and Q2 ON. JFET4 and Q6 stillproduce V_(p), so the same current level continues to be mirrored by Q1.This current is now steered through Q2 instead of Q3, producing avoltage drop across R3 in the same proportion to R2 as is the resistanceof R3 to that of R2. The R3 voltage differential is reflected across thegate-source terminals of JFET1 as described above, holding the switchsecurely OFF.

While the actual resistances of R2 and R3 are still subject toprocessing and temperature variations, the ratio of their resistancevalues can be established at a substantially invariant level bywell-known resistance matching techniques employed in integrated circuitprocessing. Similarly, the absolute value of V_(p) is subject toprocessing and temperature variations, but the matching of JFET4 andswitch JFET1 assures that the V_(p) of both elements will vary in thesame manner. The relationship between V_(p) and the OFF voltage appliedacross the gate-source terminals of JFET1 is thus dependent only on theR3/R2 ratio, which is substantially independent of both processing andtemperature variations. A considerably greater resistance value can thusbe assigned to R3 than was possible with the prior art circuit of FIG.1, resulting in a correspondingly reduced power consumption by thatelement, without jeopardizing the proper switching of JFET1.

While a particular embodiment of the invention has been shown anddescribed, numerous variations may occur to those skilled in the art.For example, any circuit other than JFET4/Q6 capable of generating aV_(p) matched with that of JFET1 could be used. As another example, thecurrent steered through the differential switch and R3 could differ inmagnitude from the current through R2, so long as the resistance valueof R3 is adjusted so that it establishes the correct voltage to beapplied to JFET1. Accordingly, it is intended that the invention belimited only in terms of the appended claims.

I claim:
 1. A lower power, process and temperature insensitive circuitfor a switch FET, said switch FET having a gate, source and drain andcharacterized by a pinch-off voltage which is subject to processing andtemperature variations, comprising:a bus for receiving a voltagepotential from a voltage source, first and second resistors having apredetermined resistance ratio and each connected to the bus, firstcircuit means connected with respect to the bus to generate a voltageacross the first resistor which is proportional to the switch FETpinch-off voltage, and thereby drive a current proportional to thepinch-off voltage through the first resistor, current reflection meansconnected to receive current from the first resistor and to drive acurrent through the second resistor which is proportional to the currentthrough the first resistor, and thereby generate a voltage across thesecond resistor which is proportional to the pinch-off voltage, switchcontrol means controlling the application of current to the secondresistor, and second circuit means connecting the bus and one end of thesecond resistor in circuit with the switch FET gate, and the other endof the second resistor with the switch FET source to impose a voltageacross the gate-source terminals of the switch FET which is controlledby the current through the second resistor and is at least equal to thepinch-off voltage when said proportional currents flow through the firstand second resistors.
 2. The circuit of claim 1, said first circuitmeans comprising a control FET matched with the switch FET, andcircuitry for establishing a pinch-off voltage across the control FET,said control FET having its gate connected in common with one end of thefirst resistor and with the bus, its source connected to the oppositeend of the first resistor, and its source and drain connected to thecircuitry for establishing a pinch-off voltage across the control FET.3. The circuit of claims 1 or 2, wherein the current reflection meanscontrols the current driven through the second resistor in response tothe current through the first resistor to produce a voltage drop acrossthe second resistor which is slightly greater than the pinch-offvoltage, and said second circuit means imposes a gate-source voltageacross the switch FET which is substantially equal to the voltage acrossthe second resistor.
 4. The circuit of claims 1 or 2, wherein saidcurrent reflection means includes a current mirror means connected tomirror the current through the first resistor and to drive asubstantially equal current through the second resistor.
 5. The circuitof claim 3, wherein the resistance of the second resistor is slightlygreater than that of the first resistor, thereby producing voltagesacross the second resistor and switch FET which are slightly greaterthan the pinch-off voltage.
 6. A low power, process and temperatureinsensitive bias circuit for a switch FET, said switch characterized bya pinch-off voltage which is subject to processing and temperaturevariations, comprising:a source of electric potential, a control FETmatched with the switch FET, means connected with respect to thepotential source for generating a pinch-off voltage across the gate andsource of the control FET, circuit means interconnecting the switch andcontrol FETs to establish a voltage across the gate-source terminals ofthe switch FET which is at least as great as the voltage across thegate-source terminals of the control FET, said circuit means includingmeans for sensing the current through the control FET and connected withrespect to the potential source to impose a voltage across thegate-source terminals of the switch FET which is proportional to thesensed voltage, an interrupt switch for disconnecting theinterconnection between the switch and control FETs, and first andsecond matched resistors, the first resistor being connected across thegate and source terminals of the control FET, whereby the currentthrough the first resistor is proportional to the gate-source voltage ofthe control FET, the second resistor being connected in a circuit withthe gate and source terminals of the switch FET such that the voltageacross the second resistor is substantially equal to the voltage acrossthe gate-source terminals of the switch FET, further circuit meansdriving a current through the second resistor in proportion to thecurrent through the first resistor, and switch control means connectedto actuate the interrupt switch and thereby disconnect theinterconnection between the control FET and switch FET in response to aswitch actuation command.
 7. The circuit of claim 6, wherein theresistance values of the first and second resistors are proportionatelymatched to establish a gate-source voltage across the switch FETslightly greater than the pinch-off voltage.
 8. A low power, process andtemperature insensitive bias circuit for a switch FET, said switchcharacterized by a pinch-off voltage which is subject to processing andtemperature variations, comprising:a bus for receiving a voltagepotential from a voltage source, a control FET matched with the switchFET and having its gate connected to the voltage bus, a first resistorconnected between the source of the control FET and the voltage bus, abipolar transistor having its base and one of its collector-emitterterminals connected across the source-drain terminals of the control FETto establish a pinch-off voltage across the control FET and the firstresistor, and its other collector-emitter terminal providing a currentoutput substantially equal to the current through the first resistor, adifferential switch having first and second branches, a current sourcefor said differential switch connected to mirror the current flowingthrough the first resistor, switch control means connected to steercurrent from said current source to one or the other of the differentialswitch branches in response to the presence or absence of an inputswitch control signal, a second resistor connected to the voltage biasline in one branch of the differential switch to receive thedifferential switch current in response to an OFF signal from the switchcontrol means, said second resistor being matched with the firstresistor to generate a voltage at least equal to the voltage across thefirst resistor in response to received differential switch current, andcircuit means including the other branch of the differential switch andconnecting the second resistor and voltage bus in circuit with theswitch FET to impose a voltage across the gate-source terminals of theswitch FET at least equal to the voltage across the second resistor,whereby a voltage at least equal to the pinch-off voltage is imposedacross the gate-source terminals of the switch FET in response to an OFFsignal from the switch control means.
 9. The circuit of claim 8, whereinthe resistance of the second resistor is slightly larger than theresistance of the first resistor, thereby establishing a voltageslightly greater than the pinch-off voltage across the gate-sourceterminals of the switch FET in response to an OFF signal from the switchcontrol means.
 10. The circuits of claims 1, 2, 6 or 8, said control andswitch FETs each comprising junction FETs.